1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a semiconductor device employing a high dielectric constant ("high-K") gate dielectric and a method for forming this device which avoids exposing the high-K dielectric to high processing temperatures. The invention further relates to a test structure for rapid and inexpensive evaluation of gate dielectric/conductor configurations, and a method for forming such a test structure.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide ("oxide"), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors and interconnects, which have less than 1.0 .mu.m critical dimension. As feature size decreases, the size of the resulting transistor as well as the interconnect between transistors also decreases. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
As MOSFET feature sizes decrease, gate oxide thickness decreases as well. This decrease in gate oxide thickness is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts.
Another factor driving reduction of gate oxide thickness is the increased transistor drain current realized for a reduced gate dielectric thickness. Higher transistor drain currents are desirable because they allow each transistor to drive a greater number of other transistors, and can result in increased switching speeds. The transistor drain current is proportional to the amount of charge induced in the transistor channel region by the voltage applied to the gate conductor. The amount of charge induced by a given voltage drop across the gate oxide is the voltage drop multiplied by the capacitance of the oxide. Increasing the capacitance of the oxide therefore increases the transistor drain current. The capacitance C of the oxide can be written as for a parallel plate capacitor: EQU C=.epsilon.A/t.sub.ox ,
where .epsilon. is the permittivity of the oxide, A is its area, and t.sub.ox is the oxide thickness. The value of the capacitance is therefore dependent upon both the thickness and the permittivity of the gate oxide.
In order to achieve increased capacitance, gate oxide thickness has been reduced so much that current oxides are on the order of ten angstroms thick. Unfortunately, thin oxide films may break down when subjected to an electric field, particularly for gate oxides less than 50 .ANG. thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through a thin gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that some of these electrons may become entrapped within the gate oxide by e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, the threshold voltage V.sub.T may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of gate voltage, as a result of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice.
A more promising approach to further increasing gate dielectric capacitance may be to increase the permittivity of the gate dielectric. Permittivity, .epsilon., of a material reflects the ability of the material to be polarized by an electric field. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, .epsilon..sub.0. Hence, the relative permittivity or dielectric constant of a material is defined as: EQU K=.epsilon./.epsilon..sub.0
While oxide has a dielectric constant of approximately 4, other materials have higher K values. Silicon nitride ("nitride"), for example, has a K of about 6 to 9 (depending on formation conditions). Much higher K values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta.sub.2 O.sub.5), barium strontium titanate ("BST"), and lead zirconate titanate ("PZT"). Using a high-K material for a gate dielectric would allow a high capacitance to be achieved even with a relatively thick dielectric. For example, a nitride gate dielectric having a thickness of 100 angstroms is substantially electrically equivalent to an oxide gate dielectric having a thickness of about 50 angstroms. For even higher-K dielectrics, even thicker gate dielectrics could be formed while maintaining capacitance values higher than are possible with even very thin oxide layers. In this way, the reliability problems associated with very thin dielectric layers may be avoided while transistor performance is increased.
Although the high K values of the metal oxide dielectrics noted above make them attractive gate dielectric candidates, integration of these materials into a MOSFET does present problems. In particular, metal and oxygen atoms from these metal oxides may diffuse into and react with an underlying silicon channel region or an overlying polysilicon gate conductor. Many metal atoms are associated with carrier trap states in silicon, so that carrier lifetime in a device may be reduced by diffusion of metal atoms into an active region of the device. Maintaining low processing temperatures may help to prevent interdiffusion of high-K materials and silicon during MOSFET fabrication. Unfortunately, typical MOSFET fabrication processes expose gate conductors and gate dielectrics to elevated temperatures in order to produce self-aligned source and drain regions. These source and drain regions exhibit minimal overlap with the transistor gate, minimizing the parasitic capacitances that limit high-frequency transistor performance. In general, the self-alignment is achieved by fabricating a gate conductor over a gate dielectric, and then using the gate conductor as a mask for introduction of dopant impurities to form the source and drain. The source and drain impurities are typically introduced using ion implantation. Because they are formed before the implantation and subsequent annealing of the source and drain impurities, the gate conductor and gate dielectric must be made from materials which can withstand high-temperature processing.
In addition to the interdiffusion problem discussed above, integration of high-K dielectrics into MOS integrated circuit production flows may present other challenges. Because movement toward high-K dielectrics in MOS processing is currently in its early stages, much experimentation will be needed to establish myriad aspects of production, such as material selection, deposition parameters, and etch techniques. Performing a complete transistor fabrication process for testing of each combination of the many variables involved is extremely expensive and time-consuming.
It would therefore be desirable to develop a technique for fabricating a transistor having a gate dielectric formed from a high-K material. The desired process should not expose the high-K material to elevated temperatures, such as those required for annealing the source and drain implants. However, the gate conductor of the transistor should be self-aligned to the transistor source and drain regions. It would further be desirable to develop a simplified method for fabrication of devices for testing of high-K dielectric materials.